Array ( [7] => stdClass Object ( [menu_label] => TICO [firstProductId] => 31 [products] => Array ( ) ) [1] => stdClass Object ( [menu_label] => JPEG 2000 FPGA/ASIC [firstProductId] => 15 [products] => Array ( [0] => stdClass Object ( [id] => 1 [menu_label] => HD Encoder/Decoder ) [1] => stdClass Object ( [id] => 2 [menu_label] => Cinema Encoder/Decoder ) [2] => stdClass Object ( [id] => 3 [menu_label] => Lossless Encoder/Decoder ) [3] => stdClass Object ( [id] => 26 [menu_label] => UHD 4K/8K Encoder/Decoder ) [4] => stdClass Object ( [id] => 34 [menu_label] => J2K-RAW Encoder/Decoder ) ) ) [3] => stdClass Object ( [menu_label] => Crypto / Security [firstProductId] => 9 [products] => Array ( [0] => stdClass Object ( [id] => 10 [menu_label] => AES Encryption ) [1] => stdClass Object ( [id] => 11 [menu_label] => RSA Public Key ) [2] => stdClass Object ( [id] => 12 [menu_label] => HMAC-SHA1 ) ) ) [2] => stdClass Object ( [menu_label] => Memory Controllers [firstProductId] => 5 [products] => Array ( [0] => stdClass Object ( [id] => 6 [menu_label] => Memory Controllers ) ) ) [10] => stdClass Object ( [menu_label] => Video Transport [firstProductId] => 38 [products] => Array ( [0] => stdClass Object ( [id] => 39 [menu_label] => MPEG-2 TS ) [1] => stdClass Object ( [id] => 41 [menu_label] => SMPTE 2022 Reference Design ) [2] => stdClass Object ( [id] => 8 [menu_label] => UDP Protocol Manager ) ) ) )

IPX-UDP: UDP Protocol Manager

General Description

The IPX-UDP receives UDP packets (including video/audio assets) on a gigabit Ethernet link.

The MAC controller is based on the Tri-Mode MAC controller that is hard-coded from the Virtex-5 SXT or LXT technology.

intoPIX configures the MAC controller with a specific MAC address read from a dedicated register and also sets up the external PHY chip.

The selected protocol (SGMII, GMII or RGMII), the exact chip reference and the corresponding user manual must be provided by the customer. To speed up the development, intoPIX recommends SGMII protocol.

The protocol handler will manage the user UDP protocol. This handler is in charge of:

• receiving video/audio packets,
• verifying the integrity with IP and UDP checksum and Ethernet CRC,
• sending a response packet back for every n packets received.

If a packet is missing or corrupted, the UDP handler will reject all subsequent packets while waiting for a correct
retransmission of its related n packet group.

Resources

Resources for Altera and Xilinx FPGA devices are provided on request.

Key Features

• Reduced footprint
• Supports Gigabit Ethernet
• Highly integrated

 

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