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DDR Memory Controllers

General Description

The IPX-DDR core is a DDR2 / DDR3 / DDR4 / LPDDR2 memory controller optimized for managing single and multiple JPEG2000 cores as well as to share processing with other IP-cores. It can be adapted to various configuration and for Xilinx or Altera devices. The Memory controller guarantees efficient DDR access to the JPEG 2000 IP-cores and is fully compatible with all the families of intoPIX JPEG 2000 IP-cores.

The physical bus width is selectable between 8, 16, 32 and 64 bits.

Resources

Resources for Altera or Xilinx FPGA devices are provided on request and depends on your JPEG2000 project configuration

Key Features

  • Configurable data memory width
  • Continuous random data accesses within the same row
  • Reduced footprint. Area is linear with respect to the data memory width
  • High operating frequency supported
  • Efficient integration with memory arbiter cores

 


 

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